The present disclosure relates generally to integrated circuit devices and, more particularly, to electrostatic discharge protection structures for integrated circuit devices.
Integrated circuit (IC) devices are vulnerable to electrostatic discharge (ESD) damage. An ESD is generated by a high field potential, which causes ‘charge-and-discharge’ events (e.g., a rapid flow of electrons between two bodies of unequal charge or between one charged body and ground, with an electronic circuit being the path of least resistance between the two). An ESD may damage an IC by causing leakage currents or functional failures, and may even destroy an IC.
Various ESD simulation models exist, including the Human Body Model (HBM) and the Machine Model (MM). Since the human body has a charge-storage capacitance and a highly conductive sweat layer, the discharge from a person's touch may be simulated with the HBM using a resistor-capacitor (or RC) circuit. A IC device should generally survive an ESD of 2000V or higher with the HBM. The MM uses an ESD simulation test based on a discharge network consisting of a charged capacitor and (nominally) zero ohms of series resistance to approximate the electrostatic discharge from a machine. An IC device should generally survive an ESD of 200V or higher with the Machine Model.
The reliability challenge presented to ICs by an ESD is complicated by the shallower junction and relatively thin gate oxide used in metal oxide semiconductor field effect transistor (MOSFET) devices. This is particularly true as IC materials and fabrication processes enable the fabrication of ICs using deep sub-micron complementary MOS (CMOS) technologies. Generally, to sustain a reasonable ESD stress in submicron CMOS ICs, ESD protection circuits are added to the ICs. In order to sustain the desired ESD voltage levels, a conventional ESD protection circuit design may use an n-type MOS transistor with a resist-protection-oxide (RPO) layer. The RPO layer blocks silicidation (e.g., an anneal that results in the formation of a low resistance metal-Si alloy that acts as a contact) on the drain region to enhance ballasting resistance for an ESD protection circuit.
To further enhance ESD protection, the channel width of ESD protection devices may be designed with larger dimensions so that more ESD current can be discharged. However, if the current does not flow through the channel uniformly (e.g., if no uniform turn-on effect occurs), a larger channel width may not provide additional protection. This may be a problem in both single and multiple finger devices. For example, if current flows through only a portion of a wider drain of a single fingered device, then the IC may be destroyed even though the drain is relatively wide. In an ESD protection device implemented using multiple fingers, damage may occur if some of the fingers fail to turn on. The failure of some fingers to turn on increases the current through the remaining fingers and may destroy the associated IC.
Accordingly, what is needed is an improved ESD protection structure for IC devices.